Technical data

VHDL instantiation of Verilog design units
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Mixed VHDL and Verilog Designs ModelSim EE/PLUS Reference Manual
v
g
encomp component declaration
vgencomp
(p79) generates a component declaration according to these rules:
Generic clause
A generic clause is generated if the module has parameters. A corresponding
generic is defined for each parameter that has an initial value that does not depend
on any other parameters.
The generic type is determined by the parameter's initial value as follows:
The default value of the generic is the same as the parameter's initial value.
Examples
Port clause
TopMod \TopMod\
top_mod top_mod
_topmod \_topmod\
\topmod topmod
\\topmod\ \topmod\
Parameter value Generic t
y
pe
integer integer
real real
string literal string
Verilo
g
parameter VHDL
g
eneric
parameter p1 = 1 - 3; p1 : integer := -2;
parameter p2 = 3.0; p2 : real := 3.000000;
parameter p3 = "Hello"; p3 : string := "Hello";
Verilo
g
identifier VHDL identifier