Technical data

VHDL instantiation of Verilog design units
ModelSim EE/PLUS Reference Manual Mixed VHDL and Verilog Designs
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VHDL and Verilog identifiers
The identifiers for the component name, port names, and generic names are the
same as the Verilog identifiers for the module name, port names and parameter
names. If a Verilog identifier is not a valid VHDL 1076-1987 identifier, it is
converted to a VHDL 1076-1993 extended identifier (in which case you must
compile the VHDL with the -93 switch). Any uppercase letters in Verilog
identifiers are converted to lowercase in the VHDL identifier, except in the
following cases:
• The Verilog module was compiled with the -93 switch. This means
vgencomp
(p79) should use VHDL 1076-1993 extended identifiers in the component
declaration to preserve case in the Verilog identifiers that contain uppercase
letters.
• The Verilog module port and generic names are not unique unless case is
preserved. In this event,
vgencomp
(p79) behaves as if the module was
compiled with the -93 switch for those names only.
Examples
If the Verilog module is compiled with -93:
Verilo
g
identifier VHDL identifier
topmod topmod
TOPMOD topmod
TopMod topmod
top_mod top_mod
_topmod \_topmod\
\topmod topmod
\\topmod\ \topmod\
Verilo
g
identifier VHDL identifier
topmod topmod
TOPMOD \TOPMOD\