Technical data

VHDL instantiation of Verilog design units

Mixed VHDL and Verilog Designs ModelSim EE/PLUS Reference Manual

VHDL instantiation of Verilog design units

Once you have generated a component declaration for a Verilog module, you can

instantiate the component just like any other VHDL component. In addition, you

can reference a Verilog module in the entity aspect of a component configuration

– all you need to do is specify a module name instead of an entity name. You can

also specify an optional architecture name, but it will be ignored because Verilog

modules do not have architectures.

Verilo

instantiation criteria

A Verilog design unit may be instantiated from VHDL if it meets the following

criteria:

• The design unit is a module (UDPs are not allowed).

• The ports are named ports (Verilog allows unnamed ports).

• The ports are not connected to bidirectional pass switches (it is not possible to

handle pass switches in VHDL).

Component declaration

A Verilog module that is compiled into a library can be referenced from a VHDL

design as though the module is a VHDL entity. The interface to the module can be

extracted from the library in the form of a component declaration by running

vgencomp

(p79). Given a library and module name,

vgencomp

(p79) writes a

component declaration to standard output.

The default component port types are:

• std_logic

• std_logic_vector

Optionally, you can choose:

• bit and bit_vector

• vl_logic and vl_logic_vector

'L' Pu0

'H' Pu1

'–' StX

std_lo

ic Verilo