Technical data

Mapping data types

ModelSim EE/PLUS Reference Manual Mixed VHDL and Verilog Designs

For Verilog states with ambiguous strength:

• bit receives '0'

• std_logic receives 'X' if either the 0 or 1 strength components are greater than or

equal to strong strength

• std_logic receives 'W' if both the 0 and 1 strength components are less than

strong strength

VHDL type bit is mapped to Verilog states as follows:

VHDL type std_logic is mapped to Verilog states as follows:

St1 '1' '1'

StX 'X' '0'

Su0 '0' '0'

Su1 '1' '1'

SuX 'X' '0'

bit Verilo

'0' St0

'1' St1

std_lo

ic Verilo

'U' StX

'X' StX

'0' St0

'1' St1

'Z' HiZ

'W' PuX

Verilo

std_lo

ic bit