Technical data

Mapping data types

Mixed VHDL and Verilog Designs ModelSim EE/PLUS Reference Manual

full Verilog state set. For example, you may wish to convert between vl_logic and

your own user-defined type. The vl_logic type is defined in the vl_types package

in the pre-compiled

verilog

library. This library is provided in the installation

directory along with the other pre-compiled libraries (

std

and

ieee

). The source

code for the vl_types package can be found in the files installed with Model

Sim

See "Installed technotes" (p28).

Verilo

states

Verilog states are mapped to std_logic and bit as follows:

Verilo

std_lo

ic bit

HiZ 'Z' '0'

Sm0 'L' '0'

Sm1 'H' '1'

SmX 'W' '0'

Me0 'L' '0'

Me1 'H' '1'

MeX 'W' '0'

We0 'L' '0'

We1 'H' '1'

WeX 'W' '0'

La0 'L' '0'

La1 'H' '1'

LaX 'W' '0'

Pu0 'L' '0'

Pu1 'H' '1'

PuX 'W' '0'

St0 '0' '0'