Technical data

Mapping data types
ModelSim EE/PLUS Reference Manual Mixed VHDL and Verilog Designs
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59
Type time is treated specially: the Verilog number is converted to a time value
according to the
‘timescale
directive of the module.
Physical and enumeration types receive a value that corresponds to the position
number indicated by the Verilog number. In VHDL this is equivalent to
T'VAL(P), where T is the type, VAL is the predefined function attribute that
returns a value given a position number, and P is the position number.
Verilo
g
parameters
The type of a Verilog parameter is determined by its initial value.
VHDL and Verilo
g
ports
The allowed VHDL types for ports connected to Verilog nets and for signals
connected to Verilog ports are:
The vl_logic type is an enumeration that defines the full state set for Verilog nets,
including ambiguous strengths. The bit and std_logic types are convenient for
most applications, but the vl_logic type is provided in case you need access to the
VHDL t
y
pe Verilo
g
t
y
pe
integer integer
real real
string string
Allowed VHDL t
y
pes
bit
bit_vector
std_logic
std_logic_vector
vl_logic
vl_logic_vector