Technical data

Separate compilers, common libraries
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Mixed VHDL and Verilog Designs ModelSim EE/PLUS Reference Manual
Separate compilers, common libraries
VHDL source code is compiled by VCOM and the resulting compiled design units
(entities, architectures, configurations, and packages) are stored in a library.
Likewise, Verilog source code is compiled by VLOG and the resulting design
units (modules and UDPs) are stored in a library.
Libraries can store any combination of VHDL and Verilog design units, provided
the design unit names do not overlap (VHDL design unit names are changed to
lower case).
See "Design Libraries" (p33) for more information about library management and
see the
vcom
(p71) and the
vlog
(p83) commands.
Mapping data types
Cross-HDL instantiation does not require any extra effort on your part. As VSIM
loads a design it detects cross-HDL instantiations – made possible because a
design unit's HDL type can be determined as it is loaded from a library – and the
necessary adaptations and data type conversions are performed automatically.
A VHDL instantiation of Verilog may associate VHDL signals and values with
Verilog ports and parameters. Likewise, a Verilog instantiation of VHDL may
associate Verilog nets and values with VHDL ports and generics. VSIM
automatically maps between the HDL data types as shown below.
VHDL
g
enerics
When a scalar type receives a real value, the real is converted to an integer by
truncating the decimal portion.
VHDL t
y
pe Verilo
g
t
y
pe
integer integer or real
real integer or real
time integer or real
physical integer or real
enumeration integer or real
string string literal