Technical data
ModelSim EE/PLUS Reference Manual Mixed VHDL and Verilog Designs -
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Mixed VHDL and Verilog Designs
Chapter contents
Separate compilers, common libraries . . . . . . . . . . . . . . 58
Mapping data types . . . . . . . . . . . . . . . . . . . 58
VHDL generics . . . . . . . . . . . . . . . . . . . 58
Verilog parameters . . . . . . . . . . . . . . . . . . 59
VHDL and Verilog ports . . . . . . . . . . . . . . . . 59
Verilog states . . . . . . . . . . . . . . . . . . . 60
VHDL instantiation of Verilog design units. . . . . . . . . . . . . 62
Verilog instantiation criteria . . . . . . . . . . . . . . . 62
Component declaration . . . . . . . . . . . . . . . . . 62
vgencomp component declaration . . . . . . . . . . . . . . 64
Verilog instantiation of VHDL design units. . . . . . . . . . . . . 65
VHDL instantiation criteria. . . . . . . . . . . . . . . . 65
SDF annotation . . . . . . . . . . . . . . . . . . . 66
Model
Sim
/Plus single-kernel simulation (SKS) allows you to simulate designs
that are written in VHDL and/or Verilog. This chapter outlines data mapping and
the criteria established to instantiate design units between HDLs.
The boundaries between VHDL and Verilog are enforced at the level of a design
unit. This means that although a design unit must be either all VHDL or all
Verilog, it may instantiate design units from either language. Any instance in the
design hierarchy may be a design unit from either HDL without restriction. SKS
technology allows the top-level design unit to be either VHDL or Verilog. As you
traverse the design hierarchy, instantiations may freely switch back and forth
between VHDL and Verilog.