Technical data

566
- Index ModelSim EE/PLUS Reference Manual
LD_LIBRARY_PATH, and SHLIB_PATH
457
MGC_HOME, and MGC_WD
457
simulator state variables
iteration number
252
name of entity or module as a variable
252
resolution
252
simulation time
252
Variables, setting
environment variables
54
modelsim.ini variables
415
simulator control variables
253
simulator preference variables (GUI)
user_hook
226
user-defined variables
256
Variables, Tcl
252
vcd add simulator command
379
vcd checkpoint simulator command
380
vcd comment simulator command
381
vcd file simulator command
382
VCD files
adding items to the file
379
dumping variable values
380
extracting the proper stimulus
492
flushing the buffer contents
384
from VHDL source to VCD output
494
inserting comments
381
specifying maximum file size
385
specifying the file name
382
state mapping
382
turn off VCD dumping
386
turn on VCD dumping
387
VCD system tasks
492
vcd flush simulator command
384
vcd limit simulator command
385
vcd off simulator command
386
vcd on simulator command
387
vcom ModelSim command
71
vcom simulator command
391
vdel ModelSim command
76
vdir ModelSim command
78
Verilog
‘uselib compiler directive
52
capturing port driver data with -dumpports
383
,
498
compiling design units
46
component declaration
64
creating a design library
46
hazard detection
50
instantiation criteria
62
instantiation of VHDL design units
65
literals in commands
50
mapping states in mixed designs
60
mixed designs with VHDL
57
object names in commands
50
parameters
59
SDF annotation
440
sdf_annotate system task
440
simulating
48
SmartModel interface
510
source code viewing
156
timing check disabling
49
Verilog PLI
483
–
486
ACC routines for VHDL objects
485
replaying a Verilog PLI session
489
specifying the PLI file to load
483
support for VHDL objects
484
TF routines and Reason flags
486
verilog project file variable
416
Veriuser project file variable
421
vgencomp ModelSim command
79
VHDL
compiling design units
46
creating a design library
46
delay file opening
424
dependency checking
47
field naming syntax
250
file opening delay
424
instantiation from Verilog
65
instantiation of Verilog
58
library clause
41
mixed designs with Verilog
57
object support in PLI
484
simulating
48
SmartModel interface
502