Technical data

564
- Index ModelSim EE/PLUS Reference Manual
creating a signal log file 325
displaying drivers of
306
displaying environment of
312
displaying in Dataflow window
127
displaying values in Signals window
150
examining values
313
finding
317
forcing signal and net values
152
indexing arrays
250
pathnames in VSIM commands
249
saving values as binary log file
154
selecting signal types to view
152
specifying force time
320
specifying radix of in List window
261
specifying radix of in Wave window
272
specifying radix of signal to examine
314
viewing waveforms
168
Signals window (see also, Windows)
150
Simulating
applying stimulus
see also VSIM command, force
applying stimulus to signals and nets
152
applying stimulus with textio
429
batch mode
532
command-line mode
532
Mixed Verilog and VHDL Designs
compilers
58
libraries
58
Verilog parameters
59
Verilog state mapping
60
VHDL and Verilog ports
59
VHDL generics
58
saving waveform as a Postscript file
188
setting default run length
208
setting iteration limit
208
setting time resolution
199
Simulation action list
27
specifying design unit
91
specifying the time unit for delays
256
stepping through a simulation
371
VHDL and Verilog designs
48
viewing results in List window
131
Simulation and Compilation 45
–
56
SmartModel, see Logic Modeling
Sockets, callback functions for (Windows)
466
Software updates
524
Sorting
sorting HDL items in VSIM windows
112
Source code
source code security
534
viewing
156
Source files
referencing with location maps
539
Source window (see also, Windows)
156
SourceDir simulator control variable
254
SourceMap simulator control variable
254
splitio simulator command
369
Stability checking
disabling
290
enabling
289
Startup
alternate to startup.do (vsim -do)
92
macro in the modelsim.ini file
420
startup macro in command-line mode
532
using a startup file
423
Startup macros
423
Startup project file variable
420
Status bar
Main window
124
status simulator command
370
std project file variable
415
std_developerskit project file variable
416
StdArithNoWarnings project file variable
420
StdArithNoWarnings simulator control variable
254
STDOUT environment variable
55
step simulator command
371
stop simulator command
372
Structure window (see also, Windows)
162
SWIFT, see Logic Modeling
Symbolic link to design libraries (UNIX)
40
synopsys project file variable
416
Syntax conventions
29