Technical data

Modeling memory in VHDL
ModelSim EE/PLUS Reference Manual Tips and Techniques
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543
architecture style_87 of memory is
begin
memory:
process (cs)
-----------------------
variable ram : ram_type;
-----------------------
variable address : natural;
begin
if rising_edge(cs) then
address := sulv_to_natural(add_in);
if (mwrite = '1') then
ram(address) := data_in;
data_out <= ram(address);
else
data_out <= ram(address);
end if;
end if;
end process;
end style_87;
architecture bad_style_87 of memory is
----------------------
signal ram : ram_type;
----------------------
begin
memory:
process (cs)
variable address : natural := 0;
begin
if rising_edge(cs) then
address := sulv_to_natural(add_in);
if (mwrite = '1') then
ram(address) <= data_in;
data_out <= data_in;
else
data_out <= ram(address);
end if;
end if;
end process;
end bad_style_87;
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