Technical data

Modeling memory in VHDL
ModelSim EE/PLUS Reference Manual Tips and Techniques
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Modeling memory in VHDL
VHDL users might be tempted to model a memory using signals. Two common
simulator problems are the likely result:
• a "memory allocation error", typically meaning the simulator ran out of memory
- it failed to allocate more storage
• very long load, elaboration or run times
These problems are usually explained by the fact that signals consume a
substantial amount of memory (many dozens of bytes per bit), all of which needs
to be loaded or initialized before your simulation starts.
A simple alternative implementation provides some excellent performance
benefits:
• storage required to model the memory can be reduced by 1-2 orders of
magnitude
• startup and run times are reduced
• associated memory allocation errors are eliminated
The trick is to model memory using variables instead of signals.
In the example below, we illustrate three alternative architectures for entity
"memory". Architecture "style_87_bad" uses a vhdl signal to store the ram data.
Architecture "style_87" uses variables in the "memory" process, and architecture
"style_93" uses variables in the architecture.
For large memories, architecture "style_87_bad" runs many times longer than the
other two, and uses much more memory. This style should be avoided.
Both architectures "style_87" and "style_93" work with equal efficiently. You’ll
find some additional flexibility with the VHDL 1993 style, however, because the
ram storage can be shared between multiple processes. For example, a second
process is shown that initializes the memory; you could add other processes to
create a multi-ported memory.
To implement this model, you will need functions that convert vectors to integers.
To use it you will probably need to convert integers to vectors.
Example functions are provided below in package "conversions".
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use std.standard.all;
library ieee;
use ieee.std_logic_1164.all;
use work.conversions.all;