Technical data

Toggle checking
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Tips and Techniques ModelSim EE/PLUS Reference Manual
Toggle checking
Toggle checking counts the number of transitions to 0 and 1 on specified nodes.
Once the nodes have been selected, a toggle report may be requested at any time
during the simulation. The toggle commands can be used on VHDL and Verilog
designs.
These toggle checking commands are in "Simulator Command Reference"
(p245):
•
toggle add
(p374)
•
toggle reset
(p375)
•
toggle report
(p376)
Detecting infinite zero-delay loops
VHDL simulation uses steps that advance simulated time, and steps that do not
advance simulated time. Steps that do not advance simulated time are called "delta
cycles". Delta cycles are used when signal assignments are made with zero time
delay.
If a large number of delta cycles occur without advancing time, it is usually a
symptom of an infinite zero-delay loop in the design. In order to detect the
presence of these loops, Model
Sim
defines a limit, the “iteration_limit", on the
number of successive delta cycles that can occur. When the iteration_limit is
exceeded, VSIM stops the simulation and gives a warning message.
You can set the iteration_limit from the
Simulation > Properties
menu, by
modifying the
modelsim.ini
file or by setting a Tcl variable called IterationLimit
(p254).
The iteration_limit default value is 5000.
When you get an iteration_limit warning, first increase the iteration limit and try
to continue simulation. If the problem persists, look for zero-delay loops.
One approach to finding zero-delay loops is to increase the iteration limit again
and start single stepping. You should be able to see the assignment statements or
processes that are looping. Looking at the Process window will also help you to
see the active looping processes.
When the loop is found, you will need to change the design to eliminate the
unstable loop.