Technical data

Bus float checking
ModelSim EE/PLUS Reference Manual Tips and Techniques
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message is also issued when the contention ends. The bus contention checking
commands can be used on VHDL and Verilog designs.
These bus checking commands are in the "Simulator Command Reference"
(p245):
•
check contention add
(p283)
•
check contention config
(p284)
•
check contention off
(p285)
Bus float checking
Bus float checking detects nodes that are in the high impedance state for a time
equal to or exceeding a user-defined limit. This is an error in some technologies.
Detection of a float violation results in an error message identifying the node. A
message is also issued when the float violation ends. The bus float checking
commands can be used on VHDL and Verilog designs.
These bus float checking commands are in "Simulator Command Reference"
(p245):
•
check float add
(p286)
•
check float config
(p287)
•
check float off
(p288)
Design stability checking
Design stability checking detects when circuit activity has not settled within a
user-defined period for synchronous designs. The user specifies the clock period
for the design and the strobe time within the period that the circuit must be stable
at. A violation is detected and an error message is issued if there are pending driver
events at the strobe time. The message identifies the driver that has a pending
event, the node that it drives, and the cycle number. The design stability checking
commands can be used on VHDL and Verilog designs.
These design stability checking commands are in "Simulator Command
Reference" (p245):
•
check stable on
(p289)
•
check stable off
(p290)