Technical data

Verilog-specific simulation issues
ModelSim EE/PLUS Reference Manual Compilation and Simulation
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into a specified library. The library thus contains pre-compiled modules and UDPs
(as well as VHDL design units) that are drawn from by the simulator as it loads
the design.
Within a library, distinct modules/UDPs are distinguished by name. Thus it's not
possible for two distinct parts to have the same name and at the same time in a
single library. From the previous example, it's not possible for both vendors'
NAND2 modules to exist within the same library.
How Model
Sim
supports ‘uselib
Model
Sim
does support the notion of multiple libraries, however. Thus it is
possible for two different NAND2's to exist in different libraries. All that is
needed is a mechanism for specifying which library should be examined for a
given NAND2 at the site of its instantiation.
Model
Sim
overloads the
‘uselib
directive for this purpose. With a little care, this
allows the same design source to be used with both Model
Sim
and other Verilog
systems.
To do this, the VLOG compiler infers one or more library paths wherever it
encounters a
‘uselib
directive. It does this by recording the directory portions of
the
‘uselib
options, and tacking a "/work" to the end of them (under the
assumption each referenced library is compiled into a local
work
library). This
path information is stored with the compiled design and is used to locate the
appropriate "NAND2" by the simulator.
The VLOG compiler does NOT compile any files implied by the
‘uselib
directive.
This is where it differs the most from other systems. It is assumed that the user has
or will compile the source libraries into a local
work
library before simulating the
design (the simulator will issue an error message if it does not encounter a library
on the inferred path).
Thus, the earlier example of a
‘uselib
directive:
‘uselib dir=/h/vendorA/FPGAlib libext=.v
would infer a library on the path
/h/vendorA/FPGAlib/work
. When the VSIM
simulator instantiates a reference to NAND2 that was under the control of this
directive, it would look in
/h/vendorA/FPGAlib/work
for the pre-compiled
NAND2 component.
Model
Sim
also extends the
‘uselib
directive by allowing a
lib=
option (multiple
lib=
options may be separated with a space). This would allow the above directive
to be more explicitly coded as:
‘uselib lib=/h/vendorA/FPGAlib/work