Technical data

Verilog-specific simulation issues
52
-
Compilation and Simulation ModelSim EE/PLUS Reference Manual
• VSIM will search inferred libraries from any
‘uselib's
in effect at compilation
time.
• VSIM will search libraries provided by any
-L <library>
option provided on
the VSIM command line. (See
vsim
(p91) for more information on the
–L
option.)
• VSIM will examine the current
work
library.
• If the referenced design unit is an escaped identifier of the form "library.name",
it will search "library" for the design unit "name".
• If the referenced design unit is an escaped identifier of the form
“library.name(arch)”, it will search "library" for the (presumably VHDL entity)
primary "name", with secondary "arch".
The Verilo
g
‘uselib compiler directive
The
‘uselib
directive is not part of the IEEE 1364 specification (neither as
required nor as "informative"), but it is supported in some Verilog systems
(including Model
Sim
) and it is the only solution to a class of instantiation binding
problems.
The
‘uselib
directive provides very similar functionality to the
vlog
(p83)
switches,
-v <library_file>
,
-y <library_directory>
, and
+libext+<suffix>
,
except it is supported in the form of a compiler directive.
Thus,
‘uselib dir=/h/vendorA/FPGAlib libext=.v
appearing in Verilog source (say,
design.v
) would be very similar to the
compilation line:
vlog design.v -y /h/vendorA/FPGAlib +libext+.v
except pathnames are included in the actual source files rather than on the
compilation line. The most significant advantage, however, is that it can be used
to control access to vendor libraries on an instance by instance basis.
To illustrate the importance of this, assume that one is trying to simulate a board
that contains 2 FPGAs from different vendors. Both vendors may very well have
cells named NAND2. The netlist for each FPGA needs to pick up the
corresponding cell from the appropriate library. It would not do for the compiled
netlist of one FPGA to attempt to use the NAND2 from the other vendor's library.
Compiled environment issues
Model
Sim
supports and encourages separate compilations of distinct portions of
the design. This methodology leads to a compiler that compiles one or more files