Technical data

Verilog SmartModel interface
510
-
Logic Modeling Library and Hardware Modeler ModelSim EE/PLUS Reference Manual
Memory arrays
A memory model usually makes the entire register array available as a window.
In this case, the window commands operate only on a single element at a time. The
element is selected as an array reference in the window instance specification. For
example, to read element 5 from the window memory
mem
:
lmcwin read /top/u2/mem(5)
Omitting the element specification defaults to element 0. Also, continuous
monitoring is limited to a single array element. The associated window signal is
updated with the most recently enabled element for continuous monitoring.
Verilog SmartModel interface
The SWIFT SmartModel Library, beginning with release r40b, provides an
optional library of Verilog modules and a PLI application that communicates
between a simulator's PLI and the SWIFT simulator interface. The Logic
Modeling documentation refers to this as the Logic Models to Verilog (LMTV)
interface. To install this option, you must select the simulator type "Verilog" when
you run SmartInstall.
LMTV usa
g
e documentation
The
SmartModel Library Simulator Interface Manual
is installed with Logic
Modeling’s software. Look for the file:
<LMC_install_dir>/doc/smartmodel/
manuals/slim.pdf
. This document is written with Cadence Verilog in mind, but
mostly applies to Model
Sim
Verilog.
Make sure you follow the instructions
below for linking the LMTV interface to the simulator.
Linkin
g
the LMTV interface to the simulator
Starting with Model
Sim
5.1, Model Technology ships a dynamically loadable
library that links Model
Sim
to the LMTV interface. To link to the LMTV all you
need to do is add
libswiftpli.sl
to the Veriuser line in
modelsim.ini
as in the
example below:
Veriuser = $MODEL_TECH/libswiftpli.sl
Compilin
g
Verilo
g
shells
Once
libswiftpli.sl
is in the
modelsim.ini
file (and you’ve restarted Model
Sim
) you
can compile the Verilog shells provided by Logic Modeling. You compile them