Technical data

Verilog-specific simulation issues
ModelSim EE/PLUS Reference Manual Compilation and Simulation
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51
You can use this feature to help you write code that ports more easily among
Verilog simulators. VSIM matches the event ordering of Cadence's Verilog
simulator in many, but not all, cases. VSIM's hazard detection is useful in porting
models that rely on Cadence Verilog event ordering.
The
vsim
command (p91) detects the following kinds of hazards:
• WRITE/WRITE:
Two processes writing to the same variable at the same time.
• READ/WRITE:
One process reading a variable at the same time it is being written to by another
process. VSIM calls this a READ/WRITE hazard if it executed the read first.
• WRITE/READ:
Same as a READ/WRITE hazard except that VSIM executed the write first.
The
vsim
command (p91) issues an error message when it detects a hazard. The
message pinpoints the variable and the two processes involved. You can have the
simulator break on the statement where the hazard is detected by setting the
break
on assertion
level to
error
.
To enable hazard detection you must invoke
vlog
(p83) with the
-hazards
option
when you compile your source code and you must also invoke
vsim
(p91) with the
-hazards
option when you simulate.
Limitations of hazard detection:
• Reads and writes involving bit and part selects of vectors are not considered for
hazard detection. The overhead of tracking the overlap between the bit and part
selects is too high.
• A WRITE/WRITE hazard is flagged even if the same value is written by both
processes.
• A WRITE/READ or READ/WRITE hazard is flagged even if the write does not
modify the variable's value.
• Glitches on nets caused by non-guaranteed event ordering are not detected.
Instantiation bindin
g
s
Verilog module and UDP instantiations are not bound to
specific design units at compilation time; instead, VSIM
dynamically binds them as a design is loaded. The VSIM
simulator performs the following steps, in order, to find a given design unit at
elaboration time:
VERILOG