Technical data

VHDL SmartModel interface
506
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Logic Modeling Library and Hardware Modeler ModelSim EE/PLUS Reference Manual
DelayRange : STRING := "Max";
MemoryFile : STRING := "memory" );
port ( A : in std_logic_vector (15 downto 0);
CS : in std_logic;
O : out std_logic_vector (7 downto 0);
WAIT_PORT : inout std_logic );
end component;
for all: cy7c285
use entity work.cy7c285
port map (A0 => A(0),
A1 => A(1),
A2 => A(2),
A3 => A(3),
A4 => A(4),
A5 => A(5),
A6 => A(6),
A7 => A(7),
A8 => A(8),
A9 => A(9),
A10 => A(10),
A11 => A(11),
A12 => A(12),
A13 => A(13),
A14 => A(14),
A15 => A(15),
CS => CS,
O0 => O(0),
O1 => O(1),
O2 => O(2),
O3 => O(3),
O4 => O(4),
O5 => O(5),
O6 => O(6),
O7 => O(7),
WAIT_PORT => WAIT_PORT );
Simulation
After you have created the entities and architectures for the SML models in your
design, you compile the design with VCOM just like any other VHDL design.
However, before invoking VSIM make sure that the LMC_HOME environment
variable is set to the root of the SmartModel Library installation tree.
During simulation, the SML models may issue messages. These messages are
posted to the Main transcript window just like assertion messages from VHDL
models. The difference is that the message header identifies the message as