Technical data

VHDL SmartModel interface
ModelSim EE/PLUS Reference Manual Logic Modeling Library and Hardware Modeler
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SM_ENTITY
To simulate an SML model with VSIM you must first create the corresponding
entity and foreign architecture. The SM_ENTITY tool is provided to automate
this task. It takes SML model names as input and writes VHDL output to stdout.
The LMC_HOME environment variable must be set to the root of the SmartModel
Library installation tree before you invoke SM_ENTITY.
The usage of SM_ENTITY is:
Syntax
sm_entity
[options] [SmartModels]
Arguments
-
read SmartModel names from standard input
-xe
do not generate entity declarations
-xa
do not generate architecture bodies
-c
generate component declarations
-all
select all models in the SmartModel library
-v
display progress messages
By default, SM_ENTITY generates an entity and architecture. Optionally, you
can include the component declaration (-c), exclude the entity (-xe), and exclude
the architecture (-xa). (See the SmartModel Library documentation for details on
SML model names.)
This command: