Technical data

ModelSim EE/PLUS Reference Manual Logic Modeling Library and Hardware Modeler -
501
14 -
Logic Modeling Library and
Hardware Modeler
Chapter contents
VHDL SmartModel interface . . . . . . . . . . . . . . . 502
SM_ENTITY . . . . . . . . . . . . . . . . . . 503
Entity details . . . . . . . . . . . . . . . . . . 505
Architecture details . . . . . . . . . . . . . . . . . 505
Vector ports. . . . . . . . . . . . . . . . . . . 505
Simulation . . . . . . . . . . . . . . . . . . . 506
SPARCstation note . . . . . . . . . . . . . . . . . 507
Command channel . . . . . . . . . . . . . . . . . 507
SmartModel Windows for VHDL . . . . . . . . . . . . . . 508
ReportStatus . . . . . . . . . . . . . . . . . . 508
SmartModel lmcwin commands . . . . . . . . . . . . . 508
Memory arrays . . . . . . . . . . . . . . . . . . 510
Verilog SmartModel interface . . . . . . . . . . . . . . . 510
Linking the LMTV interface to the simulator . . . . . . . . . . 510
Compiling Verilog shells . . . . . . . . . . . . . . . 510
Changing the default time precision . . . . . . . . . . . . 511
Logic Modeling Hardware Modeler. . . . . . . . . . . . . . 511
This chapter describes the use of the SmartModel Library, SmartModel Windows,
and the Logic Modeling Hardware Modeler with Model
Sim
.
Model
Sim
EE/PLUS supports the Logic Modeling SWIFT-based SmartModel
Library on the following platforms:
• SPARCstation with SunOS 4.1.3 or Solaris 2.x
• HP 9000 Series 700 with HP/UX 9.01
• IBM RISC System/6000 through AIX 3.2.5
• Windows NT, and 95/98
Note:
When you obtain the SWIFT-based SmartModel Library from Logic Modeling, the library will
come with documentation that describes how to use the library in general and also how to use specific models.
This chapter only describes the specifics of using the SmartModel Library with Model
Sim
EE/PLUS.