Technical data

Verilog-specific simulation issues
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Compilation and Simulation ModelSim EE/PLUS Reference Manual
By default, the timing checks within VITAL models are
enabled. They are also disabled with the
+notimingchecks
option.
For example:
vsim +notimingchecks topmod
Verilog-specific simulation issues
Verilo
g
object names in commands
By default, VSIM requires the "/" character as separators in
hierarchical names. You can use the "." character instead by
setting the PathSeparator variable (p254) to "." in the
modelsim.ini
file.
Setting extended identifiers
Verilog extended identifiers in
vsim
commands (p91)
must use the VHDL
extended identifier notation:
Start with a "\" (backslash) and end with a "\" (backslash), rather than ending with
a space. Extended identifiers in Verilog source code use the standard Verilog
notation, but will be displayed in VSIM windows using the VHDL notation.
Verilo
g
literals in commands
Verilog style literals are allowed in VSIM commands. You
may use either Verilog or VHDL style literals independent of
the type of object operated on.
For example, the following command may modify either a Verilog or VHDL
variable:
change var 'hff
Hazard detection
The
vsim
command (p91) can help you find hazards in your
Verilog code. As an option, you can have VSIM notify you
when it executes code that depends on an order of execution
that is not guaranteed by the language. This kind of hazard always involves
concurrently executing processes that are simultaneously accessing a global
variable.
VHDL
VERILOG
VERILOG
VERILOG