Technical data

Resimulating a VHDL design from a VCD file
ModelSim EE/PLUS Reference Manual Value Change Dump (VCD) Files
-
493
signal must be captured in the VCD file along with its related bidirectional port.
See the description of the
splitio
command (p369) for more details.
Specifyin
g
a filename and state mappin
g
s
After using splitio , the VCD filename and state mapping are specified using the
vcd file
command (p382) with the
-nomap -direction
options.
Note that the
-nomap
option is not necessary if the port types on the top-level
design are bit or bit_vector. It is required, however, for std_logic ports because it
records the entire std_logic state set. This allows the
-vcdread
option to duplicate
the original stimulus on the ports.
The default VCD file is
dump.vcd
, but you can specify a different filename with
vcd file. For example,
vcd file mydumpfile.vcd -direction
Creatin
g
the VCD file
After invoking vcd file you can create the new VCD file by executing
vcd add
(p379) at the time you wish to begin capturing value changes. To dump everything
in a design to a dump file you might use a command like this:
vcd add -r /*
At a minimum, the VCD file must contain the in and inout ports of the design unit.
Value changes on all other signals are ignored by
-vcdread
. This also means that
the simulation results are not checked against the VCD file.
After the VCD file is created, it can be input to
vsim
(p91) with the
-vcdread
option to resimulate the design unit stand-alone.
Example
The following example illustrates a typical sequence of commands to create a
VCD file for input to
-vcdread
. Assume that a VHDL testbench named testbench
instantiates dut with an instance name of u1, and that you would like to simulate
testbench and later be able to resimulate dut stand-alone:
vsim -c -t ps testbench
VSIM 1> splitio /u1/*
VSIM 2> vcd file -nomap -direction
VSIM 3> vcd add -ports /u1/*
VSIM 4> run 1000
VSIM 5> quit