Technical data

ModelSim EE/PLUS Reference Manual Value Change Dump (VCD) Files -
491
13 -
Value Change Dump (VCD) Files
Chapter contents
ModelSim VCD commands and VCD tasks . . . . . . . . . . . 492
Resimulating a VHDL design from a VCD file . . . . . . . . . . . 492
Extracting the proper stimulus for bidirectional ports . . . . . . . . 492
Specifying a filename and state mappings . . . . . . . . . . . 493
Creating the VCD file . . . . . . . . . . . . . . . . 493
A VCD file from source to output . . . . . . . . . . . . . . 494
VHDL source code . . . . . . . . . . . . . . . . . 494
VCD simulator commands . . . . . . . . . . . . . . . 495
VCD output . . . . . . . . . . . . . . . . . . . 495
Capturing port driver data with -dumpports. . . . . . . . . . . . 498
This chapter explains Model Technology’s Verilog VCD implementation for
Model
Sim
.
The VCD file format is specified in the IEEE 1364 standard. It is an ASCII file
containing header information, variable definitions, and variable value changes.
VCD is in common use for Verilog designs, and is controlled by VCD system task
calls in the Verilog source code. Model
Sim
provides simulator command
equivalents for these system tasks and extends VCD support to VHDL designs;
the Model
Sim
commands can be used on either VHDL or Verilog designs.