Technical data

Simulating VHDL and Verilog designs
ModelSim EE/PLUS Reference Manual Compilation and Simulation
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The default time resolution can also be changed by modifying the Resolution
variable (p420) in the
modelsim.ini
file. You can view the current resolution by
invoking the
report
command (p354) with the
simulator state
option.
See "System Initialization/Project File" (p413) for more information on
modifying the modelsim.ini file.
VSIM will set the simulation time resolution to the minimum
time precision specified by the ’timescale directives. If no
’timescale directives are found, the time resolution will be set
to the "resolution" variable setting in the
modelsim.ini
file; if this variable is not
set, the time resolution will default to 1ns. The
vsim
(p91)
-t
option or the
Load
Design
dialog box selection will override the ’timescale directives and the
modelsim.ini
file.
Min:Typ:Max and timing delay annotation
By default, VSIM selects typical delays from the min:typ:max
expressions in the Verilog code. You can explicitly select a
delay set by invoking
vsim
(p91) with the
+mindelays
,
+typdelays
, or
+maxdelays
options.
For example, to simulate with maximum delays:
vsim +maxdelays topmod
VSIM is capable of annotating a design using VITAL
compliant models or Verilog models with timing data from an
SDF file. You can specify the min:typ:max delay by invoking
vsim
(p91) with the
-sdfmin
,
-sdftyp
and
-sdfmax
options. Using the SDF file
f1.sdf
in the current work directory, the following invocation of VSIM annotates
maximum timing values for the design unit
my_asic
:
vsim -sdfmax /my_asic=f1.sdf
In addition, Verilog designs may use the
$sdf_annotate
system task in place of
the command line options to perform SDF annotation.
See "ModelSim and VITAL" (p431) for more information on VITAL and SDF.
Timing check disabling
By default, the timing check system tasks ($setup, $hold,...) in
specify blocks are enabled. They can be disabled with the
+notimingchecks
option.
VERILOG
VERILOG
VHDL &
VERILOG
VERILOG