Technical data

FLI and PLI tracing
488
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VHDL Foreign Language Interface and Verilog PLI ModelSim EE/PLUS Reference Manual
vsim -trace_foreign 1 -tag 2 mydesign
creates a log file with a tag of "2"
The tracing operations will provide tracing during all user foreign code-calls,
including VHDL foreign process call-backs, PLI user tasks and functions (calltf,
checktf, sizetf and misctf routines), and Verilog VCL call-backs. The
miscellaneous VHDL call-backs (LoadComplete, Restart, Quit, EnvChanged,
SimStatus, Save and Restore) are traced during execution but not explicitly
identified as being from a callback function in the current product.
Note:
Tracing does not work across checkpoint/restore operations. Also note that example files produced
are in the
trace.note
file located in the install directory.
Installin
g
the dummy component
for VHDL trace replay
To install the dummy component, put the following statements in your top level
architecture:
component dummy
port(...);
-- same port names and types as your top level entity
generic(...);
-- same generic names and types as your top level entity
end component;
...
dummy1 : dummy
port map(...); -- attach inputs to top level inputs
-- leave outputs OPEN
generic map(...); -- pass in top-level generics
Also, compile the following code:
entity dummy is
port(...);
-- ports and generics as in the above component decl.
generic(...);
end;
architecture initial of dummy is
begin
end;