Technical data

Using the Verilog PLI
ModelSim EE/PLUS Reference Manual VHDL Foreign Language Interface and Verilog PLI
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485
no provision for obtaining handles to generics, types, constants, attributes,
subprograms, and processes. However, some of these objects can be manipulated
through the Model
Sim
VHDL foreign interface (mti_* routines). See "VSIM
function descriptions" (p467).
PLI ACC routines for VHDL objects
The following PLI ACC routines operate on VHDL objects:
acc_collect
acc_compare_handles
acc_count
acc_fetch_defname
returns the entity and architecture name in the form "entity(architecture)" for an
architecture instance.
acc_fetch_direction
returns the direction of a port signal.
acc_fetch_fullname
acc_fetch_fulltype
acc_fetch_location
acc_fetch_name
acc_fetch_type
acc_handle_by_name
acc_handle_object
acc_handle_parent
acc_handle_scope
acc_next
acc_next_child
acc_next_net
returns signals in an architecture instance.
acc_next_port
returns port signals in an architecture instance.
acc_next_portout
returns output port signals in an architecture instance.
acc_next_scope
acc_next_topmod
acc_object_in_typelist
acc_object_of_type
acc_set_interactive_scope
acc_set_scope