Technical data

Using the Verilog PLI
484
-
VHDL Foreign Language Interface and Verilog PLI ModelSim EE/PLUS Reference Manual
The Veriuser entry also accepts a list of shared objects. Each shared object is an
independent PLI application that must contain an init_usertfs entry point that
registers the application's tasks and callback functions. An example entry in the
modelsim.ini
file is:
Veriuser = app1.so app2.so app3.so
VSIM also supports two alternative methods of specifying the PLI files to load:
the
vsim
(p91)
-pli
command line option and the PLIOBJS (p55) environment
variable.
See also
See "Compiling and linking FLI and PLI applications" (p452) for information on
compiling and linking objects for the PLI. And see "System Initialization/Project
File" (p413) for more information on the
modelsim.ini
file.
Support for VHDL objects
The PLI ACC routines also provide limited support for VHDL objects in either an
all VHDL design or a mixed VHDL/Verilog design. The following table lists the
VHDL objects for which handles may be obtained and their type and fulltype
constants:
The type and fulltype constants for VHDL objects are defined in the
acc_vhdl.h
include file. All of these objects (except signals) are scope objects that define
levels of hierarchy in the Structure window. Currently, the PLI ACC interface has
T
y
pe Fullt
y
pe Description
accArchitecture accArchitecture instantiation of an architecture
accBlock accBlock block statement
accGenerate accGenerate generate statement
accPackage accPackage package declaration
accForLoop accForLoop for loop statement
accForeign accForeign foreign scope created by mti_CreateRegion
accSignal accSignal signal declaration