Technical data

Using the Verilog PLI
ModelSim EE/PLUS Reference Manual VHDL Foreign Language Interface and Verilog PLI
-
483
VHDL FLI examples
Several examples that illustrate how to use the foreign language interface and an
include file are shipped with Model
Sim
EE.
Example one
uses these VHDL source and C code files:
example1.vhd
example1.c
Example two
uses one VHDL source code file and several C files:
foreign.vhd
dumpdes.c
gates.c
monitor.c
Example three
is an entire VHDL testbed:
test_circuit.vhd
tester.vhd
xcvr.vhd
tester.c
vectors
You’ll find the include file is at:
/<install_dir>/modeltech/mti.h
All example files are located in:
/<install_dir>/modeltech/examples/foreign/
Using the Verilog PLI
Specifyin
g
the PLI file to load
Once your C application has been compiled it is ready to be used by the PLI. The
name of the file to load is specified in the
modelsim.ini
file by the Veriuser entry.
The Veriuser entry must be in the [vsim] section of the file.
For example,
[vsim]
.
.
.
Veriuser = app.so