Technical data

Simulating VHDL and Verilog designs
48
-
Compilation and Simulation ModelSim EE/PLUS Reference Manual
entity compilation results will remain unchanged and you will not have to
recompile design units that depend on the entity.
Simulating VHDL and Verilog designs
After compiling the design units, you can proceed to simulate your designs with
VSIM. This section includes a discussion of simulation from the UNIX or
Windows/DOS command line. You can also use the graphic interface for
simulation, see "Simulating with the graphic interface" (p198).
Invokin
g
the simulator from the Main transcript window
For a Verilog design, invoke
vsim
(p91) with the name of the
top-level module, or with a list of names if there are multiple
top-level modules.
For example,
vsim top1 top2 top3
If a top-level module name is not specified, VSIM will present the
Load Design
dialog box from which you can choose one or more top-level modules. See
"Simulating with the graphic interface" (p198) for more information.
For VHDL, invoke
vsim
(p91) with the name of the
configuration, or entity/architecture pair. Note that if you
specify a configuration you may not specify an architecture.
This example invokes
vsim
(p91) on the entity
my_asic
and the architecture
structure
:
vsim my_asic structure
If a design unit name is not specified, VSIM will present the
Load Design
dialog
box from which you can choose a configuration or entity/architecture pair. See
"Simulating with the graphic interface" (p198) for more information.
Selecting the time resolution
The simulation time resolution is 1 ns by default. You can
select a specific time resolution with the
vsim
(p91)
-t
option
or from the
Load Design
dialog box. Available resolutions
are: 1x, 10x or 100x of fs, ps, ns, us, ms, or sec.
For example, to run in picosecond resolution, or 10ps resolution respectively:
vsim -t ps topmod
vsim -t 10ps topmod
VERILOG
VHDL
VHDL