Technical data

Compiling VHDL and Verilog designs
ModelSim EE/PLUS Reference Manual Compilation and Simulation
-
47
modelsim.ini
file (see "System Initialization/Project File" (p413) for more
information).
See "ModelSim Command Reference" (p67) for more information on the
vcom
command (p71).
Invokin
g
the Verilo
g
compiler
Model
Sim
compiles one or more Verilog design units
(modules and UDPs) – in any combination – with a single
invocation of
vlog
(p83), the Verilog compiler. The design
units are compiled in the order that they appear on the command line; however,
you can compile the files in any order you choose because the interface checking
among design units is deferred until the design is loaded by VSIM. Compiler
directives encountered in a file persist for all subsequent files.
See "ModelSim Command Reference" (p67) for more information on the
vlog
command (p83).
For more information on Verilog compiler directives use the
Help > Technotes
menu selection.
Desi
g
n checkin
g
VLOG performs semantic checking as each design unit is
compiled. These checks do not extend across the boundaries
of a design unit because each design unit is analyzed as an
independent unit. The interfaces among design units are not checked until the
design is loaded and elaborated by VSIM, at which time the following kinds of
checks are performed:
port and parameter associations in instantiations
• hierarchical name references to objects external to the module
• calls to user-defined and built-in system tasks and system functions
Dependency checkin
g
Dependent design units must be reanalyzed when the design
units they depend on are changed in the library. VCOM and
VLOG determine whether or not the compilation results have
changed. For example, if you keep an entity and its architectures in the same
source file and you modify only an architecture and recompile the source file, the
VERILOG
VERILOG
VHDL