Technical data

Compiling VHDL and Verilog designs
46
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Compilation and Simulation ModelSim EE/PLUS Reference Manual
Compiling VHDL and Verilog designs
Compiling is nothing new to VHDL simulation. Unlike most Verilog tools,
however, Model
Sim
provides a compiled Verilog environment – a design is first
compiled, and then simulated. This process provides significant speed
improvement over an interpreted approach and yet maintains flexibility when you
modify your design. You can compile a complete design or subset of a design in
one or more invocations of the compiler. The compile order is not critical when
compiling multiple Verilog items. However, when compiling VHDL,
dependencies between design units may require a specific compile order.
Creatin
g
a desi
g
n library
Before you can compile your design, you must create a library
to store the compilation results. Use
vlib
(p81) to create a new
library. For example:
vlib work
This creates a library named
work
. By default, compilation results are stored in
the
work
library. VHDL and Verilog design units can be compiled into the same
library.
Note:
The
work
library is actually a subdirectory named
work
. This subdirectory contains a special file
named _info. Do not create libraries using UNIX, MS Windows, or DOS commands – always use the
vlib
command (p81).
See "Design Libraries" (p33) for additional information on working with libraries.
Invokin
g
the VHDL compiler
Model
Sim
compiles one or more VHDL design units with a
single invocation of
vcom
(p71), the VHDL compiler. The
design units are compiled in the order that they appear on the
command line. For VHDL, the order of compilation is important – you must
compile any entities or configurations before an architecture that references them.
You can simulate a design containing units written with both the 1076 -1987 and
1076 -1993 versions of VHDL. To do so you will need to compile units from each
VHDL version separately. VCOM compiles units written with version 1076 -1987
by default; use the -93 option with
vcom
(p71) to compile units written with
version 1076 -1993. You can also change the default by modifying the
VHDL &
VERILOG
VHDL