Technical data

ModelSim EE/PLUS Reference Manual Compilation and Simulation -
45
3 -
Compilation and Simulation
Chapter contents
Compiling VHDL and Verilog designs . . . . . . . . . . . . . . 46
Creating a design library . . . . . . . . . . . . . . . . 46
Invoking the VHDL compiler . . . . . . . . . . . . . . . 46
Invoking the Verilog compiler . . . . . . . . . . . . . . . 47
Design checking . . . . . . . . . . . . . . . . . . 47
Dependency checking . . . . . . . . . . . . . . . . . 47
Simulating VHDL and Verilog designs . . . . . . . . . . . . . . 48
Invoking the simulator from the Main transcript window . . . . . . . . 48
Verilog-specific simulation issues . . . . . . . . . . . . . . . 50
Verilog object names in commands . . . . . . . . . . . . . 50
Verilog literals in commands . . . . . . . . . . . . . . . 50
Hazard detection . . . . . . . . . . . . . . . . . . 50
Instantiation bindings . . . . . . . . . . . . . . . . . 51
The Verilog ‘uselib compiler directive . . . . . . . . . . . . . 52
Environment variables . . . . . . . . . . . . . . . . . . 54
This chapter is an overview of compilation and simulation for VHDL and Verilog
within the Model
Sim
/PLUS environment.
As the text moves through compiling and simulating, Model
Sim
differences (and
similarities) for VHDL and Verilog are called out with the following graphics:
Many of the examples in this chapter are shown from the command line. For
compiling and simulation within ModelSim’s GUI see:
• Compiling with the graphic interface (p191)
• Simulating with the graphic interface (p198)
VHDL &
VERILOG
(both)
VHDL
(VHDL only)
VERILOG
(VERILOG only)