Technical data

SDF for Mixed VHDL and Verilog Designs
ModelSim EE/PLUS Reference Manual Standard Delay Format (SDF) Timing Annotation
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(from the timescale directive), then the path delay receives a value of 20ps. The
SDF value of 16ps is rounded to 20ps. Interconnect delays are rounded to the time
precision of the module that contains the annotated MIPD.
SDF for Mixed VHDL and Verilog Designs
Annotation of a mixed VHDL and Verilog design is very flexible. VHDL VITAL
cells and Verilog cells may be annotated from the same SDF file. This flexibility
is available only by using the simulator’s SDF command-line options. The
Verilog $sdf_annotate system task can annotate Verilog cells only. See the
vsim
command (p91) for more information on SDF command-line options.
Interconnect delays
An interconnect delay represents the delay from the output of one device to the
input of another. This type of delay is modeled in the receiving device as a delay
from an input port to an internal node. In VHDL VITAL this node is explicitly
declared, whereas in Verilog it is automatically created by the simulator and is not
visible to the user interface.
Timing checks are performed on the interconnect delayed versions of input ports.
This may result in misleading timing constraint violations because the ports may
satisfy the constraint while the delayed versions may not. If the simulator seems
to report incorrect violations, be sure to account for the effect of interconnect
delays.
Since an interconnect delay is modeled as a single delay between an input port and
an internal node, there is no convenient way to handle interconnect delays from
multiple outputs to a single input. For both VHDL VITAL and Verilog the default
is to use the value of the latest encountered delay in the SDF file. Optionally, you
may choose the minimum or maximum value of the multiple delays with the
vsim
(p91)
-multisource_delay
option:
-multisource_delay min|max|latest