Technical data

Verilog SDF
446
-
Standard Delay Format (SDF) Timing Annotation ModelSim EE/PLUS Reference Manual
match occurs if any of the explicit edges in the specify port match any of the
explicit edges implied by the SDF port. For example,
Optional conditions
Timing check ports and path delays may have optional conditions. The annotator
uses the following rules to match conditions:
• A match occurs if the SDF does not have a condition.
• A match occurs for a timing check if the SDF port condition is semantically
equivalent to the specify port condition.
• A match occurs for a path delay if the SDF condition is lexically identical to the
specify condition.
Timing check conditions are limited to very simple conditions, therefore the
annotator can match the expressions based on semantics. For example,
The conditions are semantically equivalent and a match occurs. In contrast, path
delay conditions may be complicated and semantically equivalent conditions may
not match. For example,
The annotator does not match the second condition above because the order of r1
and r2 are reversed.
Rounded timin
g
values
The SDF
TIMESCALE
construct specifies time units of values in the SDF file.
The annotator rounds timing values from the SDF file to the time precision of the
module that is annotated. For example, if the SDF TIMESCALE is 1ns and a value
of .016 is annotated to a path delay in a module having a time precision of 10ps
SDF Verilo
g
(SETUP data (posedge clock) (5)) $setup(data, edge[01, 0x] clk, 0);
SDF Verilo
g
(SETUP data (COND (reset!=1) (posedge clock)) (5)) $setup(data, posedge clk &&& (reset==0), 0);
SDF Verilo
g
(COND (r1 || r2) (IOPATH clk q (5))) if (r1 || r2) (clk => q) = 5; // matches
(COND (r1 || r2) (IOPATH clk q (5))) if (r2 || r1) (clk => q) = 5; // does not match