Technical data

Verilog SDF

445

Standard Delay Format (SDF) Timing Annotation ModelSim EE/PLUS Reference Manual

Optional ed

e specifications

Timing check ports and path delay input ports may have optional edge

specifications. The annotator uses the following rules to match edges:

• A match occurs if the SDF port does not have an edge.

• A match occurs if the specify port does not have an edge.

• A match occurs if the SDF port edge is identical to the specify port edge.

• A match occurs if explicit edge transitions in the specify port edge overlap with

the SDF port edge.

These rules allow SDF annotation to take place even if there is a difference

between the number of edge-specific constructs in the SDF file and the Verilog

specify block. For example, the Verilog specify block may contain separate setup

timing checks for a falling and rising edge on data with respect to clock, while the

SDF file may contain only a single setup check for both edges:

In this case, the cell accommodates more accurate data than can be supplied by the

tool that created the SDF file, and both timing checks correctly receive the same

value. Likewise, the SDF file may contain more accurate data than the model can

accommodate

In this case, both SDF constructs are matched and the timing check receives the

value from the last one encountered.

Timing check edge specifiers may also use explicit edge transitions instead of

posedge and negedge. However, the SDF file is limited to posedge and negedge.

The explicit edge specifiers are 01, 0x, 10, 1x, x0, and x1. The set of [01, 0x, x1]

is equivalent to posedge, while the set of [10, 1x, x0] is equivalent to negedge. A

SDF Verilo

(SETUP data (posedge clock) (5)) $setup(posedge data, posedge clk, 0);

(SETUP data (posedge clock) (5)) $setup(negedge data, posedge clk, 0);

SDF Verilo

(SETUP (posedge data) (posedge clock) (4)) $setup(data, posedge clk, 0);

(SETUP (negedge data) (posedge clock) (6)) $setup(data, posedge clk, 0);