Technical data
Verilog SDF
ModelSim EE/PLUS Reference Manual Standard Delay Format (SDF) Timing Annotation
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443
DEVICE
is matched to primitives or specify path delays:
If the SDF cell instance is a primitive instance, then that primitive’s delay is
annotated. If it is a module instance, then all specify path delays are annotated that
drive the output port specified in the DEVICE construct (all path delays are
annotated if the output port is omitted). If no specify delays are matched, then all
primitives that drive the specified output port are annotated (or all primitives that
drive any output port if the output port is omitted).
SETUP
is matched to $setup and $setuphold:
HOLD
is matched to $hold and $setuphold:
SETUPHOLD
is matched to $setup, $hold, and $setuphold:
SDF Verilo
g
(DEVICE y (5)) and u1(y, a, b);
(DEVICE y (5)) (a => y) = 0; (b => y) = 0;
SDF Verilo
g
(SETUP d (posedge clk) (5)) $setup(d, posedge clk, 0);
(SETUP d (posedge clk) (5)) $setuphold(posedge clk, d, 0, 0);
SDF Verilo
g
(HOLD d (posedge clk) (5)) $hold(posedge clk, d, 0);
(HOLD d (posedge clk) (5)) $setuphold(posedge clk, d, 0, 0);
SDF Verilo
g
(SETUPHOLD d (posedge clk) (5) (5)) $setup(d, posedge clk, 0);
(SETUPHOLD d (posedge clk) (5) (5)) $hold(posedge clk, d, 0);
(SETUPHOLD d (posedge clk) (5) (5)) $setuphold(posedge clk, d, 0, 0);