Technical data

Verilog SDF

442

Standard Delay Format (SDF) Timing Annotation ModelSim EE/PLUS Reference Manual

SDF to Verilo

construct matchin

The annotator matches SDF constructs to corresponding Verilog constructs in the

cells. Usually, the cells contain path delays and timing checks within specify

blocks. For each SDF construct, the annotator locates the cell instance and updates

each specify path delay or timing check that matches. An SDF construct may have

multiple matches, in which case each matching specify statement is updated with

the SDF timing value. SDF constructs are matched to Verilog constructs as

follows:

IOPATH

is matched to specify path delays:

INTERCONNECT

and

PORT

are matched to input port:

Both of these constructs identify a module input or inout port and create an

internal net that is a delayed version of the port. This is called a Module Input Port

Delay (MIPD). All primitives, specify path delays, and specify timing checks

connected to the original port are reconnected to the new MIPD net.

PATHPULSE

and

GLOBALPATHPULSE

are matched to specify path delays:

If the input and output ports are omitted in the SDF, then all path delays are

matched in the cell.

SDF Verilo

(IOPATH (posedge clk) q (3) (4)) (posedge clk => q) = 0;

SDF Verilo

(INTERCONNECT u1.y u2.a (5)) input a;

(PORT u2.a (5)) inout a;

SDF Verilo

(PATHPULSE a y (5) (10)) (a => y) = 0;

(GLOABLPATHPULSE a y (30) (60)) (a => y) = 0;