Technical data

Verilog SDF
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Standard Delay Format (SDF) Timing Annotation ModelSim EE/PLUS Reference Manual
If none of the generic names look like VITAL timing generic names, then perhaps
the VITAL library cells are not being used. If the generic names do look like
VITAL timing generic names but don’t match the names expected by the
annotator, then there are several possibilities:
• The vendor’s tools are not conforming to the VITAL specification.
• The SDF file was accidentally applied to the wrong instance. In this case, the
simulator also issues other error messages indicating that cell instances in the
SDF could not be located in the design.
• The vendor’s library and SDF were developed for the older VITAL 2.2b
specification. This version uses different name mapping rules. In this case,
invoke
vsim
(p91) with the
-vital2.2b
option:
vsim -vital2.2b -sdfmax /testbench/u1=myasic.sdf testbench
For more information on resolving errors see "Troubleshooting" (p448).
Verilog SDF
Verilog designs may be annotated using either the simulator command-line
options or the
$sdf_annotate
system task (also commonly used in other Verilog
simulators). The command-line options annotate the design immediately after it is
loaded, but before any simulation events take place. The
$sdf_annotate
task
annotates the design at the time that it is called in the Verilog source code. This
provides more flexibility than the command-line options.
The $sdf_annotate system task
The syntax for
$sdf_annotate
is:
Syntax
$sdf_annotate
(["<sdffile>"], [<instance>], ["<config_file>"], ["<log_file>"],
["<mtm_spec>"], ["<scale_factor>"], ["<scale_type>"]);
Arguments
"<sdffile>"
String that specifies the SDF file. Required.
<instance>
Hierarchical name of the instance to be annotated. Optional. Defaults to the instance where
the $sdf_annotate call is made.