Technical data

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Design Libraries ModelSim EE/PLUS Reference Manual
Verilog resource libraries
Model
Sim
supports and encourages separate compilation of distinct portions of a
Verilog design. This approach provides more rapid simulation loading and much
simpler commands to invoke the simulator. The VLOG compiler is used to
compile one or more source files into a specified library. The library thus contains
pre-compiled modules and UDPs (as well as VHDL design units) that are drawn
from by the simulator as it loads the design. See "Instantiation bindings" (p51).