Technical data

ModelSim EE/PLUS Reference Manual Standard Delay Format (SDF) Timing Annotation -
435
11 -
Standard Delay Format (SDF)
Timing Annotation
Chapter contents
Specifying SDF files for simulation . . . . . . . . . . . . . . 436
Instance specification . . . . . . . . . . . . . . . . 436
VHDL VITAL SDF . . . . . . . . . . . . . . . . . . 438
SDF to VHDL generic matching . . . . . . . . . . . . . 438
Verilog SDF . . . . . . . . . . . . . . . . . . . . 440
The $sdf_annotate system task . . . . . . . . . . . . . . 440
SDF to Verilog construct matching. . . . . . . . . . . . . 442
SDF for Mixed VHDL and Verilog Designs . . . . . . . . . . . 447
Interconnect delays . . . . . . . . . . . . . . . . . . 447
Troubleshooting . . . . . . . . . . . . . . . . . . . 448
Obtaining the SDF specification. . . . . . . . . . . . . . . 450
This chapter discusses Model
Sim
’s implementation of SDF (Standard Delay
Format) timing annotation. Included are sections on VITAL SDF and Verilog
SDF, plus troubleshooting.
Verilog and VHDL VITAL timing data may be annotated from SDF files by using
the simulator’s built-in SDF annotator. ASIC and FPGA vendors usually provide
tools that create SDF files for use with their cell libraries. Refer to your vendor’s
documentation for details on creating SDF files for your library. Many vendor’s
also provide instructions on using their SDF files and libraries with Model
Sim
.
The SDF specification was originally created for Verilog designs, but it has also
been adopted for VHDL VITAL designs. In general, the designer does not need to
be familiar with the details of the SDF specification because the cell library
provider has already supplied tools that create SDF files that match their libraries.
Note:
In order to conserve disk space Model
Sim
will read sdf files that were compressed using the standard
unix/gnu file compression algorithm. The filename must end with the suffix ".Z" for the decompress to work.