Technical data

ModelSim EE/PLUS Reference Manual ModelSim and VITAL -
431
10 -
Model
Sim
and VITAL
Chapter contents
Obtaining the VITAL specification and source code . . . . . . . . . 432
VITAL packages. . . . . . . . . . . . . . . . . . . 432
ModelSim VITAL compliance . . . . . . . . . . . . . . . 432
VITAL compliance checking . . . . . . . . . . . . . . 433
VITAL compliance warnings . . . . . . . . . . . . . . 433
Compiling and Simulating with accelerated VITAL packages . . . . . . . 434
This chapter covers Model
Sim
’s implementation of the VITAL (VHDL Initiative
Towards ASIC Libraries) specification for ASIC modeling. The VITAL
specification was developed by an industry-based, informal consortium with the
following in mind:
Charter:
Accelerate the availability of ASIC libraries across industry VHDL simulators.
Objective:
High-performance, accurate (sign-off quality) ASIC simulation across VITAL-compliant
EDA tools from a single ASIC vendor description.
Approach:
Define a modeling specification (in conjunction with VHDL packages) that leverages
existing practices and techniques, is compliant with IEEE Standards 1076 and 1164, and
uses the Open Verilog International (OVI) standard delay format (SDF) timing annotation.
Standardize the approved result through the IEEE.
End-Product:
• VITAL_Timing VHDL package defining standard, acceleratable timing
procedures for delay value selection, timing checks, and timing error reporting;
• VITAL_Primitives VHDL package defining standard, acceleratable primitives
for boolean and table-based functional description;
• Specification of OVI's SDF for communication of instance delay values; and,
• Model Development Specification document defining utilization of VITAL and
VHDL elements for ASIC library development.