Technical data

Project file variables
416
-
System Initialization/Project File ModelSim EE/PLUS Reference Manual
verilog any valid path; may include
environment variables
sets path to the library containing
VHDL/Verilog type mappings; default is
<install_dir>/../verilog
arithmetic any valid path; may include
environment variables
sets path to the Mentor Graphics specific
arithmetic packages
mgc_portable any valid path; may include
environment variables
sets path to the Mentor Graphics
Quick
Sim
compatible logic set
std_developerskit any valid path; may include
environment variables
sets path to the libraries for MGC
standard developer’s kit
synopsys any valid path; may include
environment variables
sets path to the accelerated arithmetic
packages
[vcom] section
Variable name Value ran
g
ePurpose
VHDL93 0, 1 if 1, turns on VHDL-1993 as the default;
normally is off
Show_source 0, 1 if 1, shows source line containing error; default
is off
Show_VitalChecksWarnings 0, 1 if 0, turns off VITAL compliance-check
warnings; default is on
Show_Warning1 0, 1 if 0, turns off unbound-component warnings;
default is on
Show_Warning2 0, 1 if 0, turns off process-without-a-wait-statement
warnings; default is on
Show_Warning3 0, 1 if 0, turns off null-range warnings; default is on.
[Library] section
Variable name Value ran
g
ePurpose