Technical data

vcd file
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Simulator Command Reference ModelSim EE/PLUS Reference Manual
vcd file
The
vcd file
command specifies the filename and state mapping for the VCD file
created by a
vcd add
command (p379). The
vcd file
command is optional. If used,
it must be issued before any
vcd add
commands.
Related Verilog task: $dumpfile
Syntax
vcd file
[<filename>] [-nomap] [-map <mapping pairs>] [-direction]
[-dumpports]
Arguments
<filename>
Specifies the name of the VCD file that is created (the default is
dump.vcd
). Optional.
-nomap
Affects only VHDL signals of type std_logic. Optional. It specifies that the values recorded
in the VCD file shall use the std_logic enumeration characters of UX01ZWLH-. This
option results in a non-standard VCD file because VCD values are limited to the four state
character set of x01z. By default, the std_logic characters are mapped as follow
-map <mapping pairs>
Affects only VHDL signals of type std_logic. Optional. It allows you to override the default
mappings. The mapping is specified as a list of character pairs. The first character in a pair
must be one of the std_logic characters UX01ZWLH- and the second character is the
character you wish to be recorded in the VCD file. For example, to map L and H to z:
vcd file -map "L z H z"
VHDL VCD VHDL VCD
Ux Wx
Xx L0
00H1
11- x
Zz