Technical data

vcd add

ModelSim EE/PLUS Reference Manual Simulator Command Reference

379

vcd add

The

vcd add

command adds the specified items to the VCD file. The allowed

items are Verilog nets and variables and VHDL signals of type bit, bit_vector,

std_logic, and std_logic_vector (other types are silently ignored). All

vcd add

commands must be executed at the same simulation time. The specified items are

added to the VCD header and their subsequent value changes are recorded in the

VCD file.

Related Verilog task: $dumpvars

Syntax

vcd add

[-r] [-in] [-out] [-inout] [-internal] [-ports] <item_name>...

Arguments

-r

Specifies that signal and port selection occurs recursively into subregions. Optional; if

omitted, included signals and ports are limited to the current region.

-in

Includes ports of mode IN. Optional.

-out

Includes ports of mode OUT. Optional.

-inout

Includes ports of mode INOUT. Optional.

-internal

Includes internal items. Optional.

-ports

Includes all ports of modes IN, OUT, or INOUT. Optional.

<item_name>

Specifies the Verilog or VHDL item to add to the VCD file. Required. Multiple items may

be specified by separating names with spaces. Wildcards are accepted.