Technical data

step
ModelSim EE/PLUS Reference Manual Simulator Command Reference
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371
step
The
step
command steps to the next HDL statement. Current values of local
variables may be observed at this time using the variables window. VHDL
procedures, functions and Verilog tasks can optionally be skipped over . When a
wait statement or end of process is encountered, time advances to the next
scheduled activity. The Process and Source windows will then be updated to
reflect the next activity.
Syntax
step
[-over] [<n>]
Arguments
-over
Specifies that VHDL procedures, functions and Verilog tasks are to be executed but treated
as simple statements instead of entered and traced line by line. Optional.
n
Any integer. Optional. Will execute ‘n’ steps before returning.
See also
run
command (p361)