Technical data

examine
ModelSim EE/PLUS Reference Manual Simulator Command Reference
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examine
The
examine
, or
exa
command, examines one or more HDL items, and displays
current values (or the values at a specified previous time) in the Main window
(p116). It optionally can compute the value of an expression of one or more items.
The following items can be examined at any time:
•
VHDL
signals and process variables
•
Verilog
nets and register variables
To examine a VHDL variable, the simulator must be paused after a
step
command
(p371), a breakpoint, or you can specify a process label with the name. To display
a previous value, specify the desired time using the
-time
option. To compute an
expression, use the
-expr
option. The
-expr
and the
-time
options may be used
together.
Syntax
examine
[-time <time>] [-delta <delta>] [-expr {<expression>}] [-fullpath]
[-<radix>] [-name] <name>...
Arguments
-time <time>
Specifies the time value between 0 and $now for which to examine the items. If an
expression is specified it will be evaluated at that time. Optional.
The item to be examined must have been logged using the
add list
command
(p260); the
log
command (p325) is not sufficient.
If the <time> field uses a unit, the value and unit must be placed in curly brackets.
For example, the following are equivalent for ps resolution:
exa -time {3.6 ns} signal_a
exa -time 3600 signal_a
If used,
-time
must be the first option.
-delta<delta>
Specifies a simulation cycle at the specified time from which to fetch the value. The default
is to use the last delta of the time step. Optional.