Technical data

ModelSim EE/PLUS Reference Manual Introduction-
28
Installed technotes
You will find additional reference information located in text files installed with
Model
Sim
EE/PLUS. You have direct access to these files from the VSIM Main
window Help menu (p120) or refer to the following directories:
<install_dir>/<modelsim_dir>/docs/technotes
a directory for general Model
Sim
technotes
<install_dir>/<modelsim_dir>/docs/html/contents.html
a Tcl syntax reference in HTML format
<install_dir>/<modelsim_dir>/examples/mixedHDL
an example of mixed VHDL and Verilog design
chapter 6 - Setting default simulation options (p207), and
Simulator preference variables (p210)
chapter 8 - Variable functions (p421)
4 - Simulate a
design
chapter 3 - Simulating VHDL and Verilog designs (p48)
chapter 5 - vsim (p91)
chapter 6 - Simulating with the graphic interface (p198)
chapter 7 - run (p361), force (p319), and step (p371)
5 - Advanced
simulation
options
chapter 9 - Using the TextIO package (p425)
chapter 10 - ModelSim and VITAL (p431)
chapter 11 - Standard Delay Format (SDF) Timing Annotation
(p435)
chapter 12 - PLI TF routines and Reason flags (p486)
chapter 13 - Resimulating a VHDL design from a VCD file (p492)
chapter 14 - VHDL SmartModel interface (p502), and
Logic Modeling Hardware Modeler (p511)
chapter 15 - Tcl commands (p514), and Tcl examples (p519)
Simulation step Refer to these chapters and their associated sections