Technical data

HDL item pathnames
250
-
Simulator Command Reference ModelSim EE/PLUS Reference Manual
Relative path names
Relative path names do not start with the path separator, and are relative to the
current environment. The current environment defaults to the first top-level entity
or module and may be changed by the environment command or by clicking on
hierarchy levels in the structure window. Each new level in the pathname is first
searched downwards relative to the current environment, but if not found is then
searched for upwards (same search rules used in Verilog hierarchical names).
Indexin
g
si
g
nals, memories and nets
VHDL array signals, and Verilog memories and vector nets can be sliced or
indexed. Indexes must be numeric, since the simulator does not know the actual
index types. Slice ranges may be represented in either VHDL or partial Verilog
syntax, irrespective of the setting of the PathSeparator variable (p254). The syntax
is
partial
Verilog because the range must be contained within parentheses and not
in Verilog square brackets. For example,
mysignal(31:0)
specifies a slice of an array item in partial Verilog syntax.
Name case sensitivity
Name case sensitivity is different for VHDL and Verilog. VHDL names are not
case sensitive except for extended identifiers in VHDL 1076-1993. In contrast, all
Verilog names are case sensitive.
Names in VSIM commands are case sensitive when matched against case
sensitive identifiers, otherwise they are not case sensitive.
Namin
g
fields in VHDL si
g
nals
Fields in VHDL record signals can be specified using the form:
signal_name.field_name
Examples:
S
y
ntax Description
clk specifies the item clk in the current environment
/top/clk specifies the item clk in the top-level design unit.
/top/block1/u2/clk specifies the item clk, two levels down from the top-level design unit