Technical data

HDL item pathnames
ModelSim EE/PLUS Reference Manual Simulator Command Reference
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Examples
‘b11111110
8‘b11111110
‘Hffca23
21‘H1fca23
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HDL item pathnames
VHDL and Verilog items are organized hierarchically. Each of the following HDL
items creates a new level in the hierarchy:
•
VHDL
component instantiation statement, block statement, and package
•
Verilog
module instantiation, named fork, named begin, task and function
Multiple levels in a pathname
Multiple levels in a pathname are separated by the character specified in the
PathSeparator variable. The default is "/", but it can be set to any single character,
such as "." for Verilog naming conventions, or ":" for VHDL IEEE 1076-1993
naming conventions. See the PathSeparator variable (p254) for more information.
Absolute path names
Absolute path names begin with the path separator character. The first name in the
path should be the name of a top-level entity or module, but if you leave it off then
the first top-level entity or module will be assumed. VHDL designs only have one
top-level, so it doesn't matter if it is included in the pathname. For example, if you
are referring to the signal CLK in the top-level entity named top, then both of the
following pathnames are correct:
/top/clk
/clk
Note:
Since Verilog designs may contain multiple top-level modules, a path name may be ambiguous if
you leave off the top-level module name.